The present invention relates in general to circuits for generating and controlling computer clocks.
Phase-locked loops (PLL""s) have been widely used in high-speed communication systems because PLL""s efficiently perform clock recovery or clock generation at a relatively low cost. Dynamic voltage and frequency scaling is a critical capability in reducing power consumption of power sensitive devices. Scaling, in this sense, means the ability to select high performance with nominal power supply voltages and high frequency clock operation or low performance by reducing the power supply voltage and corresponding the clock frequency. Reducing the system power is usually done when performance is not needed or when running from a limited energy source such as a battery. To allow low power operation, the PLL and other circuits must support very aggressive power/energy management techniques. For the PLL this means low power operation while supporting key required features such as dynamic frequency scaling, dynamic voltage scaling, clock freezing and alternate low frequency clocking. Dynamic implies that the PLL is able to support changes in the output frequency and logic supply voltage without requiring the system to stop operation or waiting for the PLL clock to reacquire lock.
Using a PLL or delay-locked loop (DLL) has advantages in a battery powered system because a PLL is able to receive a lower frequency reference frequency from a stable oscillator to generate system clock frequencies. A PLL also allows changing the system clock frequency without changing the reference frequency.
In switching between two or more clocks in a PLL or other logic system it is important that the switching be glitch-free. Transients that occur on a clock in a computer system that is not one of the useable edges may be mistaken by the logic system as a valid clock edge and thus create timing problems or system failures. If the two or more clocks are synchronous, which means they are derived from the same reference source, providing glitch-free switching is simpler to achieve. However, if the two or more clocks are not synchronous, glitch-free switching is more difficult. In many logic systems, and in particular PLL clock systems used in a system that employs frequency scaling, there are times when it may be advantageous to switch between asynchronous clocks for the system clock while providing glitch-free switching.
There is, therefore, a need for a logic circuit that is able to switch between two or more clocks that may be synchronous or asynchronous.
A glitch-free clock selector operates to select between asynchronous clock signals in response to a select command. In one embodiment of the present invention, a two-input multiplexer (MUX) receives a clock A and a clock B. A select signal selects clock A when it is in one logic state and clock B when it is in the other logic state. The MUX output switches immediately to a clock signal based on the state of the select signal. The MUX output is combined in a logic AND gate with a latched compare signal that compares the present state of the select signal to a new state of the select signal and generates a logic one when they compare and a logic zero when they do not. At the time the new state of the select signal is latched, the present state of the select signal and the new state do not compare. The compare signal is latched when the output of the MUX transitions to a logic zero de-gating an AND logic gate, generating the clock output, and forcing the clock output to stay at its logic zero state. The new state of the select signal is also latched as the MUX select signal which switches the MUX output to the new clock. When the new clock transitions to a logic one, the select signal is latched generating the xe2x80x9cpresent statexe2x80x9d of the select signal. At this time the new state and the present state of the select signal compare and the compare signal goes to a logic one. The new compare is latched on the negative transition of the MUX output (when the new clock goes low). The logic AND gate is enabled by the new latched compare signal at the time the MUX output is a logic zero. When the MUX output makes its next positive transition, the clock output is guaranteed to start on the same transition providing glitch-free clock selection. Another embodiment of the present invention selects between more than two asynchronous clocks. In this embodiment selection is made by more than one select signal. The select signals are selectively latched in registers. The outputs of the registers are compared in a multi-bit digital comparator that generates a compare logic signal depending on the results of the compare. The compare signal is latched on the negative transition of the MUX output. The select signals are decoded in a decoder to generate select signals that control a MUX with more than two inputs. The output of the MUX is combined in a logic AND gate to guarantee that the clock output is de-gated low when the present clock is at a low level following a change in the select signals, and enabled when a new selected clock is also at a low state. The clock output is therefore guaranteed to be glitch-free during clock switching.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.